NDLI: F-gate: a device for glitch power minimization

Content Provider	IEEE Xplore Digital Library
Author	Benini, L. Macii, A. Macii, E. Poncino, M. Scarsi, R.
Copyright Year	1998
Description	Author affiliation: Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy (Benini, L.)
Abstract	Gate freezing is an innovative technique for glitch power minimization in logic circuits. The method is based on the idea of transforming some selected high-glitching gates into modified devices, called F-gates, that are able to filter out spurious transitions whenever a proper control signal is activated. The availability of an efficient implementation, in terms of performance, of the modified gates is the key in making the technique applicable in practice. We discuss design issues and explore the characteristics of F-gates. From our analysis we can conclude that F-gates can be safely used in practice as glitch filtering elements, and can thus be fruitfully exploited by the gate freezing optimization paradigm.
Starting Page	1047
Ending Page	1051
File Size	488186
Page Count	5
File Format	PDF
ISBN	0780351487
ISSN	10586393
DOI	10.1109/ACSSC.1998.751422
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-11-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Minimization CMOS logic circuits Circuit simulation Delay estimation Logic circuits Filters Automatic control Availability Filtering Power dissipation
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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