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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kuhlmann, M. Parhi, K.K. |
| Copyright Year | 1998 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA (Kuhlmann, M.) |
| Abstract | The discrete cosine transform (DCT) is widely used in image and video compression systems. Two popular approaches to implementation of DCT algorithms include use of distributed arithmetic and flow-graphs based on fast algorithms. The distributed arithmetic architectures (DAA) have been widely used in many system implementations, due to their low latency and area requirements. However, no systematic study of power, area and latency tradeoffs of the DAA and the FGA have been studied. This paper presents a systematic study of area, latency and power consumption of these two alternate architectures. It is concluded that the flow-graph architecture consumes about 39% less power compared to the distributed arithmetic architecture, at the expenses of 28% more area and a 3.75 times increase in latency. Alternatively, by reducing the level of pipelining in the flowgraph architecture the implementation consumes 13% less power, at the expense of 20% more area and a tow times increase in latency. These results have been obtained by estimating the power consumption on actual layouts with effects of parasitic capacitance included as opposed to estimation of power consumption on schematics. |
| Starting Page | 1214 |
| Ending Page | 1219 |
| File Size | 824590 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780351487 |
| ISSN | 10586393 |
| DOI | 10.1109/ACSSC.1998.751519 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1998-11-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Arithmetic Discrete cosine transforms Delay Energy consumption Video compression Matrix decomposition Computer architecture HDTV Pipeline processing Costs |
| Content Type | Text |
| Resource Type | Article |
| Subject | Signal Processing Computer Networks and Communications |
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