NDLI: Optimal design of a Half-Wave Cockroft-Walton Voltage Multiplier with minimum total capacitance

Content Provider	IEEE Xplore Digital Library
Author	Kobougias, I.C. Tatakis, E.C.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Patras, Patras (Kobougias, I.C.; Tatakis, E.C.)
Abstract	The half-wave Cockroft-Walton voltage multiplier (H-W C-W VM) is one of the most common AC-DC step-up topologies, known for its large voltage gain and its high efficiency. However, over the worldwide bibliography, the most of H-W C-W VM designers persist in using equal capacitances in every stage without considering an optimal design. The aim of this paper is to introduce a new designing method of H-W C-W VM that lays both on the choice of the adequate capacitance values to minimize the output voltage drop and ripple (so the voltage gain is maximized) as well as the calculation of the optimal number of stages that is necessary to produce the desired output voltage with the minimum total capacitance. The theoretical analysis is validated by PSPICE simulations and experimental results, accomplished on laboratory prototypes.
Starting Page	1104
Ending Page	1109
File Size	373422
Page Count	6
File Format	PDF
ISBN	9781424416677
ISSN	02759306
DOI	10.1109/PESC.2008.4592077
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-15
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Optimized production technology Capacitance Equations Gain Artificial neural networks Capacitors Integrated circuit modeling
Content Type	Text
Resource Type	Article

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