NDLI: Stress analysis and lifetime estimation on power MOSFETs for automotive ABS systems

Content Provider	IEEE Xplore Digital Library
Author	Testa, A. De Caro, S. Panarello, S. Patane, S. Letor, R. Russo, S. Poma, S. Patti, D.
Copyright Year	2008
Description	Author affiliation: DFMTFA - DCIIM, Univ. of Messina, Messina (Testa, A.; De Caro, S.; Panarello, S.; Patane, S.)
Abstract	Stress analysis and lifetime estimation are required in order to guarantee higher and higher levels of reliability of automotive power electronic devices. Stress analysis is oriented to investigate the effects of all the possible physical cause of failures, according to the defined device mission. On the basis of the stress analysis, and of a suitable reliability model a life time prediction can be performed. This is useful to predict the suitability of the device under evaluation to the prescribed mission, as well as to improve the design of new generations of devices. An experimental technique is exploited in this paper to evaluate the stress exerted on planar power MOSFETs designed to equip automotive ABS systems. The technique is based on an accurate experimental analysis of electro-thermal cycles, exploiting a laboratory tool tailored around an infrared microscope. It enables an high resolution dynamic temperature mapping with a large bandwidth. Such a tool makes also possible the evaluation of the effects of charge trapping phenomena occurring on power MOSFETS as result of unavoidable gate overvoltages. According to a reliability model based on the Coffin Manson law, finally it is shown that gate voltage spikes can dramatically reduce the expected life time.
Starting Page	1169
Ending Page	1175
File Size	1368485
Page Count	7
File Format	PDF
ISBN	9781424416677
ISSN	02759306
DOI	10.1109/PESC.2008.4592088
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-15
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Stress MOSFETs Temperature measurement Charge carrier processes Aluminum Surface discharges
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Stress induced leakage current under NBT Stress in p-MOSFETs fabricated with 65nm technologies

Stress-induced performance enhancement in Si ultra-thin body FD-SOI MOSFETs: Impacts of scaling

A new eye on NBTI-induced traps up to device lifetime using on the fly oxide trap method

Hot-carrier to cold-carrier device lifetime modeling with temperature for low power 40nm Si-bulk NMOS and PMOS FETs

Bias temperature instability investigation of double-gate FinFETs

Degradation rate for surface pitting in GaN HEMT

Modeling of DCIV recombination currents using a multistate multiphonon model

Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

Analysis and prediction of stability in commercial, 1200 V, 33A, 4H-SiC MOSFETs

Stress analysis and lifetime estimation on power MOSFETs for automotive ABS systems

Similar Documents

Stress induced leakage current under NBT Stress in p-MOSFETs fabricated with 65nm technologies

Stress-induced performance enhancement in Si ultra-thin body FD-SOI MOSFETs: Impacts of scaling

A new eye on NBTI-induced traps up to device lifetime using on the fly oxide trap method

Hot-carrier to cold-carrier device lifetime modeling with temperature for low power 40nm Si-bulk NMOS and PMOS FETs

Bias temperature instability investigation of double-gate FinFETs

Degradation rate for surface pitting in GaN HEMT

Modeling of DCIV recombination currents using a multistate multiphonon model

Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

Analysis and prediction of stability in commercial, 1200 V, 33A, 4H-SiC MOSFETs

Stress analysis and lifetime estimation on power MOSFETs for automotive ABS systems