NDLI: Characterization and optimization of inorganic spin on glass process for inter-metal dielectric using field emission scanning electron microscopy

Content Provider	IEEE Xplore Digital Library
Author	Hashim, U. Ayub, R.M.
Copyright Year	2002
Description	Author affiliation: MIMOS Semicond., Kuala Lumpur, Malaysia (Hashim, U.; Ayub, R.M.)
Abstract	Spin on Glass (SOG), an interlayer dielectric material applied in inorganic liquid form to fill narrow gaps in the subdielectric surface for planarization, is an alternative to silicon dioxide using CVD processes and CMP processes. SOG has similar electrical properties with SiO/sub 2/ as an intermetal dielectric layer. In this experiment the main features looked for are cracking, gaps, conformity and smoothness. In this respect, an experiment was setup and three different SOG process schemes were investigated. The first and the third scheme executed were using the same SOG process procedure but the SOG liquid was spun on at two different speed, 2600 and 700 rpm respectively. Whereby the second scheme again followed the same SOG process procedure as the first scheme but repeated three times for thicker SOG. The result obtained indicated that the Spin on Glass process was optimized using the third scheme and the results achieved are no cracks, no gaps and smooth features. Slow ramping rate couple with single SOG process was found to be the best scheme for SOG to smoothness the topography of the intermetal dielectric. In this scheme, SOG was spun on at the speed of 700 rpm and the sequence of the temperature treatment was 80/spl deg/C, 150/spl deg/C and 250/spl deg/C using hotplate on the SOG machine and 400/spl deg/C using vertical furnace. The result revealed that SOG spin speed at 2600 rpm was too high for SOG to adequately fill the gaps. Multiple SOG process to increase the thickness is not possible due to the cracking that occurs because of the thermal stress.
Sponsorship	Mems Technol.(M) Sdn, Bhd Kriptic Devices (M) Sdn Bhd IEEE Electron Devices Soc
Starting Page	485
Ending Page	489
File Size	542529
Page Count	5
File Format	PDF
ISBN	0780375785
DOI	10.1109/SMELEC.2002.1217871
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-19
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Glass Electron emission Scanning electron microscopy Thermal stresses Dielectric materials Surface cracks Surface topography Planarization Silicon compounds Temperature
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimization of spin-on-glass process for multilevel metal interconnects

Reduction of Cracking in Tl(TVS) Single Crystals

Silicon based micro-scale metal grid for field emission device

Planarization process using a multi-coating of spin-on-glass

High resolution scanning electron microscopy using field-emitted spin polarized electrons

In situ planarization of dielectric surfaces using boron oxide

Integration of field emitters into scanning probe microscopy sensors using focused ion and electron beams

Stylus profiler monitors chemical mechanical planarization performance

A Three-Dimensional Dynamic Simulation of Borophosphosilicate Glass Flow

Characterization and optimization of inorganic spin on glass process for inter-metal dielectric using field emission scanning electron microscopy

Similar Documents

Optimization of spin-on-glass process for multilevel metal interconnects

Reduction of Cracking in Tl(TVS) Single Crystals

Silicon based micro-scale metal grid for field emission device

Planarization process using a multi-coating of spin-on-glass

High resolution scanning electron microscopy using field-emitted spin polarized electrons

In situ planarization of dielectric surfaces using boron oxide

Integration of field emitters into scanning probe microscopy sensors using focused ion and electron beams

Stylus profiler monitors chemical mechanical planarization performance

A Three-Dimensional Dynamic Simulation of Borophosphosilicate Glass Flow

Characterization and optimization of inorganic spin on glass process for inter-metal dielectric using field emission scanning electron microscopy