NDLI: A single clock cycle MIPS RISC processor design using VHDL

Content Provider	IEEE Xplore Digital Library
Author	Reaz, M.B.I. Islam, M.S. Sulaiman, M.S.
Copyright Year	2002
Description	Author affiliation: Fac. of Eng., Multimedia Univ., Selangor, Malaysia (Reaz, M.B.I.; Islam, M.S.; Sulaiman, M.S.)
Abstract	This paper describes a design methodology of a single clock cycle MIPS RISC Processor using VHDL to ease the description, verification, simulation and hardware realization. The RISC processor has fixed-length of 32-bit instructions based on three different format R-format, I-format and J-format, and 32-bit general-purpose registers with memory word of 32-bit. The MIPS processor is separated into five stages: instruction fetch, instruction decode, execution, data memory and write back. The control unit controls the operations performed in these stages. All the modules in the design are coded in VHDL, as it is very useful tool with its concept of concurrency to cope with the parallelism of digital hardware. The top-level module connects all the stages into a higher level. Once detecting the particular approaches for input, output, main block and different modules, the VHDL descriptions are run through a VHDL simulator, followed by the timing analysis for the validation, functionality and performance of the designated design that demonstrate the effectiveness of the design.
Sponsorship	Mems Technol.(M) Sdn, Bhd Kriptic Devices (M) Sdn Bhd IEEE Electron Devices Soc
Starting Page	199
Ending Page	203
File Size	314655
Page Count	5
File Format	PDF
ISBN	0780375785
DOI	10.1109/SMELEC.2002.1217806
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-19
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Reduced instruction set computing Process design Hardware Design methodology Registers Decoding Concurrent computing Analytical models Timing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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