NDLI: Morphing Bus: A rapid deployment computing architecture for high performance, resource-constrained robots

Content Provider	IEEE Xplore Digital Library
Author	D'Souza, C. Byung Hwa Kim Voyles, R.
Copyright Year	2007
Description	Author affiliation: Electr. Eng., Minnesota Univ., Minneapolis, MN (D'Souza, C.; Byung Hwa Kim)
Abstract	For certain applications, field robotic systems require small size for cost, weight, access, stealth or other reasons. Small size results in constraints on critical resources such as power, space (for sensors and actuators), and computing cycles, but these robots still must perform many of the challenging tasks of their larger brethren. The need for advanced capabilities such as machine vision, application-specific sensing, path planning, self localization, etc. is not reduced by small-scale applications, but needs may vary with the task. As a result, when resources are constrained, it is prudent to configure the robot for the task at hand; both hardware and software. We are developing a reconfigurable computing subsystem for resource-constrained robots that allows rapid deployment of statically configured hardware and software for a specific task. The use of a field programmable gate array (FPGA) provides flexibility in hardware for both sensor interfacing and hardware-accelerated computation. In this paper, we describe a static reconfiguration architecture we call the morphing bus that allows the rapid assembly of sensors and dedicated computation through reusable hardware and software modules. It is a novel sensor bus in the fact that no bus interface circuitry is required on the sensor side - the bus "morphs" to accommodate the signals of the sensor
Sponsorship	IEEE Robotics and Automation Soc
Starting Page	311
Ending Page	316
File Size	634406
Page Count	6
File Format	PDF
ISBN	1424406013
ISSN	10504729
DOI	10.1109/ROBOT.2007.363805
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-10
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High performance computing Computer architecture Robot sensing systems Hardware Orbital robotics Sensor arrays Field programmable gate arrays Costs Actuators Machine vision
Content Type	Text
Resource Type	Article
Subject	Artificial Intelligence Control and Systems Engineering Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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