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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nakamura, H. |
| Copyright Year | 2013 |
| Description | Author affiliation: IBM Res. Tokyo, Tokyo, Japan (Nakamura, H.) |
| Abstract | The tunneling field-effect-transistor (TFET) is very promising for low power CMOS devices due to a steep subthreshold slope typically lower than 60mV/dec. One of the major issues with this structure is the surface states at the gate dielectric interface. In this study a nanowire TFET with InAs-GaSb heterojunction is numerically simulated to examine the ballistic carrier transport affected by those interface sites. By introducing dangling bonds into the GaSb surface atoms, several bound states emerge inside the bandgap. The off-state transmission exhibits sharp peaks at the energy levels of those bound states, which suggests a resonant interband tunneling process from the drain into the channel through the interface traps. This results in an off-state leakage current with no phonon scattering processes. The impact on the gate efficiency and delay time is also discussed based on the interface trap capacitor. |
| Sponsorship | IEEE Nanotechnol. Counc. |
| Starting Page | 837 |
| Ending Page | 840 |
| File Size | 1346919 |
| Page Count | 4 |
| File Format | |
| ISSN | 19449399 |
| e-ISBN | 9781479906765 |
| DOI | 10.1109/NANO.2013.6720817 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-08-05 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Tunneling Capacitors Photonic band gap Heterojunctions Delays Performance evaluation |
| Content Type | Text |
| Resource Type | Article |
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