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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ibrahim, W. Beg, A. Beiu, V. |
| Copyright Year | 2011 |
| Description | Author affiliation: Department of Computer Engineering, Faculty of Information Technology, United Arab Emirates University, Al Ain, UAE (Ibrahim, W.; Beg, A.; Beiu, V.) |
| Abstract | Full adders (FAs) are essential for digital circuits including microprocessors, digital signal processors, and microcontrollers. Both the power consumption and the reliability of FAs are crucial as they directly affect: arithmetic logic units, floating-point units, as well as memory address calculations. This paper studies the effect threshold voltage (V) variations play on the reliability of a classical 28-transistor FA, and shows that reliability can be enhanced without increasing the occupied area, and while also reducing power consumption. An enabling transistor sizing scheme is used to improve on reliability without increasing power consumption (as reducing and limiting currents). The proposed FA in 16nm predictive technology model (PTM) is significantly more reliable (six orders of magnitude in case of Cout, and three orders of magnitude in case of Sum at 10% input variations) and dissipates 38× less than a classical FA, while being 6× slower. |
| Starting Page | 500 |
| Ending Page | 503 |
| File Size | 781584 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457715143 |
| ISSN | 19449399 |
| e-ISBN | 9781457715167 |
| e-ISBN | 9781457715150 |
| DOI | 10.1109/NANO.2011.6144434 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-15 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuit reliability MOSFETs CMOS integrated circuits Logic gates reliability Full adder CMOS power energy |
| Content Type | Text |
| Resource Type | Article |
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