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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Huang, C.J. Lee, S.C. |
| Copyright Year | 2011 |
| Description | Author affiliation: Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, 10617, China (Huang, C.J.; Lee, S.C.) |
| Abstract | The heavily doped n-type silicon nanowires (SiNWs) junctionless field effect transistors (JLFETs) are fabricated using the self-aligned process to control the position and direction of SiNWs. Aligned SiNWs are grown across the pre-patterned source and drain under the assistance of the externally applied electric field, which facilitate the subsequent device fabrication. The JLFET exhibits an electron mobility ∼ 90 $cm^{2}/Vsec,$ on/off ratio ∼ $10^{7},$ and subthreshold slope ∼ 100 mV/dec. Furthermore, the current variation under stress is investigated. It is shown that stress-induced current change reaches maximum when the JLFET is operated in pinch-off condition. Finally, improvement of off current by 98% and subthreshold swing by 15% using compressive stress of 100MPa in the n-type JLFET is achieved. |
| Starting Page | 134 |
| Ending Page | 138 |
| File Size | 550228 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781457715143 |
| ISSN | 19449399 |
| e-ISBN | 9781457715167 |
| e-ISBN | 9781457715150 |
| DOI | 10.1109/NANO.2011.6144312 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-15 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon Logic gates Stress Nanowires Doping Piezoresistance MOSFET circuits strained silicon junctionless field effect transistor (JLFET) self-aligned process silicon nanowires |
| Content Type | Text |
| Resource Type | Article |
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