NDLI: Failure analysis using LVP for tolerant design about BEOL parasitic effects in nanoscale technology

Content Provider	IEEE Xplore Digital Library
Author	Jung-Tae Kim Yong-Seop Kim Moo-Jong Hong Yun-Woo Lee Eun-Chul Lee Gab-Soo Han
Copyright Year	2011
Description	Author affiliation: Samsung Electronics Co., Ltd. Semiconductor Business, System LSI Division, Product Engineering Group, San #24, Nongseo-dong, Giheung-gu, Yongin-City, Gyeonggi-Do, Korea 449-711 (Jung-Tae Kim; Yong-Seop Kim; Moo-Jong Hong; Yun-Woo Lee; Eun-Chul Lee; Gab-Soo Han)
Abstract	In nanoscale technology, parasitic effects by Backend of line (BEOL) according to feature sizes shrinkage have been reported as main issue of chip failure in VLSI designs. The timing defect failure and signal integrity problem such as crosstalk occur most frequently in deep submicron technologies. However, the root causes of timing defect and signal integrity problem are very difficult to diagnose in comparison with other stuck defects because they can be changed by external factors. This paper presents an efficient failure analysis method for initial yield ramp up and ongoing product with laser voltage probing (LVP) technology. We also describe several case studies on the failure analysis for design error improvement and yield enhancement. First, we identified the root cause of SCAN hold time failure at high voltage. In particular, several signal paths lead to unexpected timing defect failure such as crosstalk delay. Next, a crosstalk switch failure is defined as coupled interference from signal lines to a logically unrelated signal line. We analyzed failure of e-fuse data affected by BEOL crosstalk noise. The failure phenomenon is irregularly caused by test patterns, layout of signal line and applied voltage. In this paper, our FA results are contributed to providing guides for tolerant design about BEOL parasitic effects in nanoscale technology.
Starting Page	1
Ending Page	5
File Size	880147
Page Count	5
File Format	PDF
ISBN	9781457701597
ISSN	19461550
e-ISBN	9781457701580
DOI	10.1109/IPFA.2011.5992755
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-04
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Crosstalk Clocks Failure analysis Delay Flip-flops Very large scale integration
Content Type	Text
Resource Type	Article

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