NDLI: A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation

Content Provider	IEEE Xplore Digital Library
Author	Lijun Li Tropper, C.
Copyright Year	2008
Description	Author affiliation: Sch. of Comput. Sci., McGill Univ., Montreal, QC (Lijun Li; Tropper, C.)
Abstract	We describe, in this paper, a multiway partitioning algorithm for parallel gate level Verilog simulation. The algorithm is an extension of a multi-level algorithm which only creates two partitions. Like its predecessor, it takes advantage of the design hierarchy present in a Verilog circuit design. The information it makes use of is contained in the modules and their instances. The algorithm makes use of a hypergraph model of the Verilog design in which a vertex in the hypergraph represents a module instance. Our new algorithm relies upon a metric whose function is to balance the load and the communications between the modules of the Verilog design. pre-simulation is used to to evaluate the partitioning metric. When compared to hMetis, a well known multilevel partitioning algorithm, our algorithm produces a superior speedup and a reduced cut-size.
Starting Page	438
Ending Page	445
File Size	155738
Page Count	8
File Format	PDF
ISBN	9780769533742
ISSN	01903918
DOI	10.1109/ICPP.2008.89
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Partitioning algorithms Algorithm design and analysis Logic gates Integrated circuit modeling Hardware design languages Load modeling Program processors Partitioning distrubuted simulation Verilog
Content Type	Text
Resource Type	Article

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