NDLI: Thermal Management for 3D Processors via Task Scheduling

Content Provider	IEEE Xplore Digital Library
Author	Xiuyi Zhou Yi Xu Yu Du Youtao Zhang Jun Yang
Copyright Year	2008
Description	Author affiliation: Electr. & Comput. Eng., Pittsburgh Univ., Pittsburgh, PA (Xiuyi Zhou; Yi Xu)
Abstract	A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and reduce the delay of interconnects across the dies. However, a major challenge in 3D technology is the increased power density which brings the concern of heat dissipation within the processor. High temperatures trigger voltage and frequency throttlings in hardware which degrade the chip performance. Moreover, high temperatures impair the processorpsilas reliability and reduce its lifetime. To alleviate this problem, we propose in this paper an OS-level scheduling algorithm that performs thermal-aware task scheduling on a 3D chip. Our algorithm leverages the inherent thermal variations within and across different tasks, and schedules them to keep the chip temperature low. We observed that vertically adjacent dies have strong thermal correlations, and the scheduler should consider them jointly. Our proposed algorithm can remove on average 54% of hardware DTMs and result in 7.2% performance improvement over the base case.
Starting Page	115
Ending Page	122
File Size	559133
Page Count	8
File Format	PDF
ISBN	9780769533742
ISSN	01903918
DOI	10.1109/ICPP.2008.51
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three dimensional displays Heating Switches Scheduling Stacking Processor scheduling Hardware
Content Type	Text
Resource Type	Article

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