NDLI: Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures

Content Provider	IEEE Xplore Digital Library
Author	Loew, J. Ponomarev, D.
Copyright Year	2008
Description	Author affiliation: Dept. of Comput. Sci., State Univ. of New York at Binghamton, Binghamton, NY (Loew, J.; Ponomarev, D.)
Abstract	We propose a low complexity mechanism for accelerating memory-bound threads on SMT processors without adversely impacting the performance of other concurrently running applications. The main idea is to provide a two-level organization of the Reorder Buffer (ROB), where the first level is comprised of small private per-thread ROBs which are used in the normal course of execution in the absence of last level cache misses. The second ROB level is a much larger storage that can be used on demand by threads experiencing last level cache misses. The key feature of our scheme is that the allocation of the second-level ROB partition occurs to a thread experiencing a miss into the last level cache only if the number of instructions dependent on the missing load is below a predetermined threshold. We introduce a novel low-complexity mechanism to count the number of load-dependent instructions and propose two schemes for allocating second level ROB: predictive and reactive. Our results demonstrate about 30% improvement over DCRA resource distribution mechanism in terms of "harmonic mean of weighted IPCs" metric.
Starting Page	182
Ending Page	189
File Size	339791
Page Count	8
File Format	PDF
ISBN	9780769533742
ISSN	01903918
DOI	10.1109/ICPP.2008.24
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resource management Registers Program processors US Department of Defense Throughput Benchmark testing Art
Content Type	Text
Resource Type	Article

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