NDLI: A Performance Counter Based Workload Characterization on Blue Gene/P

Content Provider	IEEE Xplore Digital Library
Author	Ganesan, K. John, L. Salapura, V. Sexton, J.
Copyright Year	2008
Description	Author affiliation: Univ. of Texas at Austin, Austin, TX (Ganesan, K.; John, L.)
Abstract	IBM's Blue Gene/P, the second generation of the Blue Genesupercomputer is designed with a Universal Performance Counter (UPC) Unit at each node capable of monitoring 256 events concurrently, unlike many microprocessors that provide only a few performance counters. In this paper we demonstrate the efficacy of the interface library that we have developed, taking advantage of the UPC unit, enabling users to effortlessly instrument applications and get a profound insight into its execution on the Blue Gene/P system which could scale in thousands of nodes. The interface library allows the user to monitor about 512 performance related events out of a total of 1024 possible events and aggregate the data collected at different nodes and compute meaningful metrics through data mining.Using the developed interface, we instrumented the NAS parallel benchmarks and collected the performance counter data. We studied the MFLOPS, L3-DDR Traffic and the dynamic instruction mix based on the counters in the FPU and the cache hierarchy for different compiler optimizations, modes of operations of the system and different L3, L2 configurations for the NAS benchmarks. Our analysis identifies that compiler optimization O5 along with "-qarch440d", which uses the architectural information of the chip in optimization, is very effective in incorporating a lot of SIMD instructions and results in the most efficient execution of the benchmarks. The experiments on the L3 size indicate that an L3 size of 4MB is optimal for the NAS benchmarks and they do not benefit by increasing it further. Also, the virtual node mode of operation of the Blue Gene/P system is very effective and yields superior performance for the selected benchmarks taking advantage of the chip multiprocessor architecture of the quad-core HPC chip.
Starting Page	330
Ending Page	337
File Size	1786576
Page Count	8
File Format	PDF
ISBN	9780769533742
ISSN	01903918
DOI	10.1109/ICPP.2008.57
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radiation detectors Monitoring Libraries Program processors Instruments Benchmark testing Optimization Computer Architecture Performance Counters Performance Evaluation Supercomputing High Performance Computing
Content Type	Text
Resource Type	Article

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