NDLI: An Energy Efficient Parallel Architecture Using Near Threshold Operation

Content Provider	IEEE Xplore Digital Library
Author	Dreslinski, R.G. Bo Zhai Mudge, T. Blaauw, D. Sylvester, D.
Copyright Year	2007
Description	Author affiliation: Univ. of Michigan, Ann Arbor (Dreslinski, R.G.; Bo Zhai; Mudge, T.; Blaauw, D.; Sylvester, D.)
Abstract	Subthreshold circuit design, while energy efficient, has the drawback of performance degradation. To retain the excellent energy efficiency while reducing performance loss, we propose to investigate near subthreshold techniques on chip multiprocessors (CMP). We show that logic and memory cells have different optimal supply and threshold voltages, therefore we propose to allow the cores and memory to operate in different voltage regions. With the memory operating at a different voltage, we then explore the design space in which several slower cores clustered together share a faster LI cache. We show that an architecture such as this is optimal for energy efficiency. In particular, SPLASH2 benchmarks show a 53% energy reduction over the conventional CMP approach (70% energy reduction over a single core machine). In addition we explore the design trade-offs that occur if we have a separate instruction and data cache. We show that some applications prefer the data cache to be clustered while the instruction cache is kept private to the core allowing further energy savings of a 77% reduction over a single core machine.
Starting Page	175
Ending Page	188
File Size	958245
Page Count	14
File Format	PDF
ISBN	9780769529448
ISSN	1089795X
DOI	10.1109/PACT.2007.4336210
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-15
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy efficiency Parallel architectures Performance loss Threshold voltage Logic Space exploration Circuit synthesis Degradation Optimal control Voltage control
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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