NDLI: Reconfigurable energy efficient near threshold cache architectures

Content Provider	IEEE Xplore Digital Library
Author	Dreslinski, R.G. Chen, G.K. Mudge, T. Blaauw, D. Sylvester, D. Flautner, K.
Copyright Year	2008
Description	Author affiliation: Univ. of Michigan - Ann Arbor, Ann Arbor, MI (Dreslinski, R.G.; Chen, G.K.; Mudge, T.; Blaauw, D.; Sylvester, D.) \|\| ARM Ltd., Cambridge (Flautner, K.)
Abstract	Battery life is an important concern for modern embedded processors. Supply voltage scaling techniques can provide an order of magnitude reduction in energy. Current commercial memory technologies have been limited in the degree of supply voltage scaling that can be performed if they are to meet yield and reliability constraints. This has limited designers from exploring the near threshold operating regions for embedded processors. Summarizing prior work we show how proper sizing of memory cells can guarantee that the memory cell reliability in the near threshold supply voltage region matches that of a standard memory cell. However, this robustness comes with a significant area cost. We show how to employ these cells to build cache architectures that greatly reduce energy consumption. We propose an embedded processor based on these new cache architectures that operates in a low power mode, with minimal impact on full performance runtime. The proposed cache uses near threshold tolerant cache ways to reduce access energy combined with traditional cache ways to maintain performance. The access policy of the cache ways is then dynamically reconfigured to obtain energy efficient performance while minimally impacting the high performance mode runtime. Using near threshold cache architectures we show an energy reduction of 53% over a traditional filter cache. For the MIBench embedded benchmarks we show on average an 86% (7.3times) reduction in energy while in low power (10 MHz) mode with only an average 2% increase in runtime in high performance (400 MHz) mode. And for SpecInt applications we show a 77% (4.4times) reduction in energy in low power mode with only an average 4.8% increase in runtime for high performance mode. In addition we show that these trends hold from 130 nm to 45 nm technology nodes.
Starting Page	459
Ending Page	470
File Size	1121493
Page Count	12
File Format	PDF
ISBN	9781424428366
ISSN	10724451
DOI	10.1109/MICRO.2008.4771813
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-08
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy efficiency Runtime Threshold voltage Maintenance Batteries Robustness Logic Frequency Costs Energy consumption
Content Type	Text
Resource Type	Article

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