NDLI: Rotating Register Allocation for Enhanced Pipeline Scheduling

Content Provider	IEEE Xplore Digital Library
Author	Suhyun Kim Soo-Mook Moon
Copyright Year	2007
Description	Author affiliation: IBM T.J. Watson Res. Center, Seoul (Suhyun Kim)
Abstract	A rotating register file is a compiler-managed hardware renaming mechanism for overcoming the cross-iteration register overwrite problem in software pipelining [3J. It has primarily been used for software pipelining of straight-line and if-converted loops in the context of modulo scheduling. This paper proposes using rotating registers for software pipelining of loops with arbitrary control flows, in the context of enhanced pipeline scheduling (EPS). EPS can achieve a tight, variable initiation interval for such loops, but generates many hard-to-delete copies for handling the cross-iteration register overwrite problem. These copies may- cause a stall if they renamed multi-latency instructions, in addition to taking resources. In the prior work [9], these copies were removed by loop unrolling using an abstraction called extended live range (ELR). In this paper, we eliminate those copies by allocating rotating registers using the same ELR yet with a different interpretation, since both techniques share a similar intuition for copy elimination. There are some differences in building and using ELRs, though, which will also be discussed. We also discuss how existing rotating register allocation techniques cannot be easily adapted for EPS to handle loops with control flows. Our experimental results indicate that we can eliminate 50% of otherwise uncoalescible copies via rotating register allocation, which allows us to avoid a serious slowdown from latency handling and resource pressure without code expansion as in unrolling.
Starting Page	60
Ending Page	72
File Size	450672
Page Count	13
File Format	PDF
ISBN	9780769529448
ISSN	1089795X
DOI	10.1109/PACT.2007.4336200
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-15
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Parallel architectures Moon Hardware Resource management Delay Interference constraints VLIW
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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