NDLI: Early Register Release for Out-of-Order Processors with RegisterWindows

Content Provider	IEEE Xplore Digital Library
Author	Quinones, E. Parcerisa, J.-M. Gonzalez, A.
Copyright Year	2007
Description	Author affiliation: Univ. Polytech. de Catalunya, Barcelona (Quinones, E.; Parcerisa, J.-M.; Gonzalez, A.)
Abstract	Register windows is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements are normally increased for out-of-order execution because it requires registers for the in-flight instructions, in addition to the architectural ones. However, a large register file has an important cost in terms of area and power and may even affect the cycle time. In this paper we propose two early register release techniques that leverages register windows to drastically reduce the register requirements, and hence reduce the register file cost. Contrary to the common belief that out-of-order processors with register windows would need a large physical register file, this paper shows that the physical register file size may be reduced to the bare minimum by using this novel microarchitecture. Moreover, our proposal has much lower hardware complexity than previous approaches, and requires minimal changes to a conventional register window scheme. Performance studies show that the proposed technique can reduce the number of physical registers to the same number as logical registers plus one (minimum number to guarantee forward progress) and still achieve almost the same performance as an unbounded register file.
Starting Page	225
Ending Page	234
File Size	741082
Page Count	10
File Format	PDF
ISBN	9780769529448
ISSN	1089795X
DOI	10.1109/PACT.2007.4336214
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-15
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Out of order Registers Costs Proposals Hardware Microarchitecture Runtime Parallel architectures Pipeline processing Banking
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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