NDLI: Optimizing loop performance for clustered VLIW architectures

Content Provider	IEEE Xplore Digital Library
Author	Yi Qian Carr, S. Sweany, P.
Copyright Year	2002
Description	Author affiliation: Dept. of Comput. Sci., Michigan Technol. Univ., Houghton, MI, USA (Yi Qian; Carr, S.)
Abstract	Modem embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-performance embedded processor with high ILP generally puts large demands on register resources, making it difficult to maintain a single, multi-ported register bank. To address this problem, some architectures, e.g. the Texas Instruments TMS320C6x, partition the register bank into multiple banks that are each directly connected only to a subset of functional units. These functional unit/register bank groups are called clusters. Clustered architectures require that either copy operations or delay slots be inserted when an operation accesses data stored on a different cluster In order to generate excellent code for such architectures, the compiler must not only spread the computation across clusters to achieve maximum parallelism, but also must limit the effects of intercluster data transfers. Loop unrolling and unroll-and-jam enhance the parallelism in loops to help limit the effects of intercluster data transfers. In this paper we describe an accurate metric for predicting the intercluster communication cost of a loop and present an integer-optimization problem that can be used to guide the application of unroll-and-jam and loop unrolling considering the effects of both ILP and intercluster data transfers. Our method achieves a harmonic mean speedup of 1.4-1.7 on software pipelined loops for both a simulated architecture and the TI TMS320C64x.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput Archit. IEEE Comput. Soc. Tech. Committee on Parallel Process. ACM Special Interest Group on Comput. Architecture IFIP WG 10.3 IBM Microsoft Res. Univ. Virginia Dept. Comput. Sci
Starting Page	271
Ending Page	280
File Size	289135
Page Count	10
File Format	PDF
ISBN	0769516203
ISSN	1089795X
DOI	10.1109/PACT.2002.1106026
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VLIW Registers Parallel processing Computer architecture Costs Modems Embedded system Energy consumption Instruments Delay effects
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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