NDLI: Implementing malleability on MPI jobs

Content Provider	IEEE Xplore Digital Library
Author	Utrera, G. Corbalan, J. Labarta, J.
Copyright Year	2004
Description	Author affiliation: Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain (Utrera, G.; Corbalan, J.; Labarta, J.)
Abstract	Parallel jobs are characterized for having processes that communicate and synchronize with each other frequently. A processor allocation strategy widely used in parallel supercomputers is space-sharing, that is assigning a processors partition to each job for its exclusive use. We present a global solution to offer virtual malleability on message-passing parallel jobs, by applying a processor allocation strategy, the Folding by JobType (FJT). This technique is based on folding and moldability concepts and tries to decide the optimal initial number of processes, when to fold jobs and the number of folding times by analyzing the current and past system information. At processor level, we apply co-scheduling. We implement and evaluate the FJT under several workloads with different job sizes, classes and machine utilization. Results show that the FJT adapts easily to load changes, and can obtain better performance than the rest evaluated, on workloads with high coefficient variation and especially with burst arrivals.
Sponsorship	IEEE TCCP IEEE TCCA ACM SIGARCH IFIP WG 10.3 Conseil Regional PACA Conseil General des Alpes Maritimes IBM IBM France Intel Microsoft Sun France
Starting Page	215
Ending Page	224
File Size	296883
Page Count	10
File Format	PDF
ISBN	0769522297
ISSN	1089795X
DOI	10.1109/PACT.2004.1342555
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-03
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Supercomputers Libraries Concurrent computing Information analysis Processor scheduling Yarn Proposals Application specific processors Parallel architectures
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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