NDLI: Static placement, dynamic issue (SPDI) scheduling for EDGE architectures

Content Provider	IEEE Xplore Digital Library
Author	Ramadass Nagarajan Kushwaha, S.K. Burger, D. McKinley, K.S. Lin, C. Keckler, S.W.
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci., Texas Univ., Austin, TX, USA (Ramadass Nagarajan; Kushwaha, S.K.; Burger, D.; McKinley, K.S.; Lin, C.; Keckler, S.W.)
Abstract	Technology trends present new challenges for processor architectures and their instruction schedulers. Growing transistor density increases the number of execution units on a single chip, and decreasing wire transmission speeds causes long and variable on-chip latencies. These trends severely limit the two dominant conventional architectures: dynamic issue superscalars, and static placement and issue VLIWs. We present a new execution model in which the hardware and static scheduler instead work cooperatively, called static placement dynamic issue (SPDI). This paper focuses on the static instruction scheduler for SPDI. We identify and explore three issues SPDI schedulers must consider - locality, contention, and depth of speculation. We evaluate a range of SPDI scheduling algorithms executing on an explicit data graph execution (EDGE) architecture. We find that a surprisingly simple one achieves an average of 5.6 instructions-per-cycle (IPC) for SPEC2000 64-wide issue machine, and is within 80% of the performance without on-chip latencies. These results suggest that the compiler is effective at balancing on-chip latency and parallelism, and that the division of responsibilities between the compiler and the architecture is well suited to future systems.
Sponsorship	IEEE TCCP IEEE TCCA ACM SIGARCH IFIP WG 10.3 Conseil Regional PACA Conseil General des Alpes Maritimes IBM IBM France Intel Microsoft Sun France
Starting Page	74
Ending Page	84
File Size	335383
Page Count	11
File Format	PDF
ISBN	0769522297
ISSN	1089795X
DOI	10.1109/PACT.2004.1342543
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-03
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dynamic scheduling VLIW Delay Processor scheduling Computer architecture Hardware Wire Scheduling algorithm Out of order Laboratories
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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