NDLI: Architectural support for high speed protection of memory integrity and confidentiality in multiprocessor systems

Content Provider	IEEE Xplore Digital Library
Author	Shi, W. Lee, H.-H.S. Ghosh, M. Lu, C.
Copyright Year	2004
Description	Author affiliation: Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA (Shi, W.; Lee, H.-H.S.)
Abstract	Recently there is a growing effort in both the architecture and the security community to create a hardware solution for authenticating system memory. As shown in the previous work, hardware-based memory authentication becomes a vital component for creating future trusted computing environments and digital rights protection. Almost all these prior work have focused on authenticating memory exclusively owned by a single processing element. However, in today's computing platforms, memory is often shared by multiple processing elements that support a shared system memory with a snooping cache coherence protocol. Authenticating shared memory is a new challenge to memory protection. In this paper, we present a secure and fast architecture for authenticating shared memory. In terms of incorporating memory authentication into the processor pipeline, we propose a new scheme called authentication speculative execution. Unlike the prior approaches, our scheme does not compromise security for performance. The novel ASE scheme is not only secure as it is combined with a onetime-pad (OTP) based memory encryption but also efficient to tolerate authentication latency by executing unauthenticated instructions speculatively. Results using modified RSIM running SPLASH2 benchmark show only 5% overhead in performance on dual and quad processor platforms. Furthermore, ASE shows 80% better performance on average over conservative nonspeculative execution based authentication schemes. The scheme is of practical use for both multiprocessor systems and uni-processor systems where memory is shared by one main processor and other co-processors on the system bus.
Sponsorship	IEEE TCCP IEEE TCCA ACM SIGARCH IFIP WG 10.3 Conseil Regional PACA Conseil General des Alpes Maritimes IBM IBM France Intel Microsoft Sun France
Starting Page	123
Ending Page	134
File Size	408221
Page Count	12
File Format	PDF
ISBN	0769522297
ISSN	1089795X
DOI	10.1109/PACT.2004.1342547
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-03
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protection Multiprocessing systems Authentication Computer architecture Security Hardware Protocols Pipelines Cryptography Delay
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems

I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems

Memory Protection in Multiprocessing Systems

Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems (2004)

Architecture Support for High Speed Protection of Memory Integrity and Confidentiality in Symmetric Multiprocessor Systems (2004)

Architectural support for uniprocessor and multiprocessor active memory systems

Towards the Issues in Architectural Support for Protection of Software Execution (2004)

Improving Cost, Performance, and Security of Memory Encryption and Authentication

Fast Secure Communications in Shared Memory Multiprocessor Systems

Architectural support for high speed protection of memory integrity and confidentiality in multiprocessor systems

Similar Documents

Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems

I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems

Memory Protection in Multiprocessing Systems

Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems (2004)

Architecture Support for High Speed Protection of Memory Integrity and Confidentiality in Symmetric Multiprocessor Systems (2004)

Architectural support for uniprocessor and multiprocessor active memory systems

Towards the Issues in Architectural Support for Protection of Software Execution (2004)

Improving Cost, Performance, and Security of Memory Encryption and Authentication

Fast Secure Communications in Shared Memory Multiprocessor Systems

Architectural support for high speed protection of memory integrity and confidentiality in multiprocessor systems