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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ertl, M.A. Gregg, D. |
| Copyright Year | 2004 |
| Description | Author affiliation: Technische Univ. Wien, Austria (Ertl, M.A.) |
| Abstract | JIT compilers produce fast code, whereas interpreters are easy to port between architectures. We propose to combine the advantages of these language implementation techniques as follows: we generate native code by concatenating and patching machine code fragments taken from interpreter-derived code (generated by a C compiler); we completely eliminate the interpreter dispatch overhead and accesses to the interpreted code by patching jump target addresses and other constants into the fragments. In this paper we present the basic idea, discuss some issues in more detail, and present results from a proof-of-concept implementation, providing speedups of up to 1.87 over the fastest previous interpreter-based technique, and performance comparable to simple native-code compilers. The effort required for retargeting our implementation from the 386 to the PPC architecture was less than a person-day. |
| Sponsorship | IEEE TCCP IEEE TCCA ACM SIGARCH IFIP WG 10.3 Conseil Regional PACA Conseil General des Alpes Maritimes IBM IBM France Intel Microsoft Sun France |
| Starting Page | 41 |
| Ending Page | 50 |
| File Size | 296938 |
| Page Count | 10 |
| File Format | |
| ISBN | 0769522297 |
| ISSN | 1089795X |
| DOI | 10.1109/PACT.2004.1342540 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-10-03 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Testing Educational institutions Computer languages Program processors Turning Optimizing compilers Parallel architectures |
| Content Type | Text |
| Resource Type | Article |
| Subject | Theoretical Computer Science Hardware and Architecture Software |
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