NDLI: Simplified FPGA-based data acquisition system for PET

Content Provider	IEEE Xplore Digital Library
Author	Laymon, C.M. Miyaoka, R.S. Park, B.K. Lewellen, T.K.
Copyright Year	2003
Description	Author affiliation: Univ. of Washington, Seattle, WA, USA (Laymon, C.M.; Miyaoka, R.S.; Park, B.K.; Lewellen, T.K.)
Abstract	A data acquisition system for a single-ring, high-resolution, small-animal PET scanner is described. This single-ring test system is part of the development of a multi-ring scanner. The system was designed to be as simple (short development cycle, and low cost) and as flexible as possible while maintaining high performance standards necessary for high-resolution quantitative studies. Unlike the multi-ring system electronics under developments the test system does not use a clock, but identifies coincidences by overlapping logic signals. The ring consists of up to 18 multi-crystal MiCE modules, each of which is coupled to a resistive summing board that produces two X and two Y position signals. These are sent to the inputs of an analog multiplexer circuit. Total energy signals are also produced and used as inputs to NIM discriminators. A field programmable gate array (FPGA) is used for all system logic functions. This allows software development, testing, implementation, and modification of logic circuitry without hardware modification. Inputs to the FPGA are the outputs of the 18 discriminators. The FPGA logic produces and locks an event signal whenever two modules along allowed lines of response trigger within a preset resolving time. The FPGA also produces detector codes identifying the detectors involved in the event. These are recorded and also sent to the multiplexer to switch the position signals from the modules involved in the event to a buffered CAMAC ADC system for digitization. A "not busy" signal from the ADC is used to reset the FPGA releasing the locked signals allowing further event acquisition.
Starting Page	704
Ending Page	707
File Size	426789
Page Count	4
File Format	PDF
ISBN	0780376366
DOI	10.1109/NSSMIC.2002.1239421
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Data acquisition Positron emission tomography Field programmable gate arrays Logic testing System testing Electronic equipment testing Multiplexing Programmable logic arrays Circuit testing Event detection
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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