NDLI: Physical implementation of 3D integrated solenoids within silicon substrate for hybrid IC applications

Content Provider	IEEE Xplore Digital Library
Author	Duplessis, M. Tesson, O. Neuilly, F. Tenailleau, J.R. Descamps, P.
Copyright Year	2009
Description	Author affiliation: NXP Semiconductors, 2 Esplanade Anton Philips, Campus Effiscience, Colombelles BP 20000, 14906 Caen, Cedex 9, France (Duplessis, M.; Tesson, O.) \|\| IPDiA, 2 rue de la Girafe, 14000 Caen, France (Neuilly, F.; Tenailleau, J.R.) \|\| LaMIPS, Laboratoire commun NXP-CRISMAT, UMR 6508 CNRS ENSICAEN UCBN, 2, rue de la Girafe BP 5120, F-14079 Caen Cedex 5, France (Descamps, P.)
Abstract	This paper presents an original concept of a 3D solenoid realized in a 300μm depth High Resistivity Silicon (HRS) substrate using the Through Silicon Via (TSV) interconnection technology. Electrical performances deduced from two-ports S-parameters are reported. A comparison is performed considering first conventional O-shaped planar BiCMOS (Al Back-end) inductor, then a CMOS (45nm node, Cu Back-end) O-shaped inductor respect to area occupation together with electrical performances. A predictive electrical model is proposed and compared to measurement results. Correlations between simulation and measurements are found satisfactory.
Starting Page	1006
Ending Page	1009
File Size	418511
Page Count	4
File Format	PDF
ISBN	9781424447480
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-29
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	EUMA
Subject Keyword	Solenoids Silicon Application specific integrated circuits Hybrid integrated circuits Inductors Conductivity Through-silicon vias CMOS technology Scattering parameters BiCMOS integrated circuits
Content Type	Text
Resource Type	Article

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