NDLI: Real-Time Simulation of Permanent Magnet Motor Drive on FPGA Chip for High-Bandwidth Controller Tests and Validation

Content Provider	IEEE Xplore Digital Library
Author	Dufour, C. Abourida, S. Belanger, J. Lapointe, V.
Copyright Year	2006
Description	Author affiliation: Opal-RT Technol., Montreal, Que. (Dufour, C.; Abourida, S.; Belanger, J.; Lapointe, V.)
Abstract	Presented is a real-time simulator of a permanent magnet synchronous motor (PMSM) drive implemented on an FPGA card. Real-time simulation of PMSM drives enable thorough testing of control strategies and rapid deployment of vehicular or industrial applications. The PMSM model is based on Park transform with a reference frame on the rotor and assumes sinusoidal flux induction. A 3-phase IGBT inverter drives the PMSM machine. Both models are implemented with the RT-LAB real-time simulation platform of Opal-RT Technologies using a Simulink blockset called Xilinx System Generator (XSG), and without any VHDL coding. The paper explains various aspects of the design of the motor drive models in fixed-point representation in XSG, as well as actual simulation validation against a standard PMSM drive model built in Simulink. The PMSM drive, along with a test source for the pulse width modulation, is coded for an FPGA card. The model has user-selectable dead time, modulation index, source angle offset, and frequency. The overall model compilation and simulation is entirely automated by RT-LAB. The drive can also run in a closed loop with a controller executing on a CPU of a real-time simulator. The final PMSM drive model runs with a 20-ns integration time step, allows for time multiplexing of d-q values, and has an I/O latency of 310 ns (250 ns for the PMSM machine alone). The drive is directly connected to RT-LAB digital inputs and analog outputs (1 microsecond settling time) on the FPGA card and has a resulting total hardware-in-the-loop latency of 1.31 microseconds
Starting Page	4581
Ending Page	4586
File Size	463994
Page Count	6
File Format	PDF
ISBN	1424403901
ISSN	1553572X
DOI	10.1109/IECON.2006.347676
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-11-06
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Permanent magnet motors Field programmable gate arrays Testing Pulse width modulation Delay Electrical equipment industry Industrial control Rotors Insulated gate bipolar transistors Pulse width modulation inverters
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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