NDLI: Reconfigurable OPB Coprocessors for a Microblaze Self-Reconfigurable SOC Mapped on Spartan-3 FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Canto, E. Fons, F. Lopez, M.
Copyright Year	2006
Description	Author affiliation: Dept. of Electron., Electr. & Autom. Eng., Univ. Rovira i Virgili (Canto, E.; Fons, F.)
Abstract	Dynamically reconfigurable FPGAs are usually based on internal SRAM configuration memory, that can be fully or partially written from an external device. One of their applications is to map reconfigurable coprocessors, so an external microprocessor can change during run-time the coprocessor mapped on a FPGA. Coprocessors can execute the time-critical tasks of an algorithm, while the general purpose microprocessor executes the rest of computations and controls the FPGA reconfiguration. Microblaze is a soft-core 32-bit microprocessor designed to be implemented as a part of a system-on-chip (SOC) mapped on Xilinx FPGAs. The Xilinx EDK software allows designers to map a SOC composed of a Microblaze plus several OPB (on-chip peripheral bus) peripherals. But the EDK was not designed to allow reconfigurable OPB peripherals mapped on the FPGA device. This paper demonstrates that it is possible to design an self-reconfigurable SOC mapped on a low-cost Spartan-3 FPGA, where an area section is devoted to map several reconfigurable OPB coprocessors in a time-multiplexed way
Starting Page	4940
Ending Page	4944
File Size	220509
Page Count	5
File Format	PDF
ISBN	1424403901
ISSN	1553572X
DOI	10.1109/IECON.2006.347730
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-11-06
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Coprocessors Field programmable gate arrays Microprocessors Random access memory Runtime Software design Programming profession Read-write memory Application software Time factors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in