NDLI: Vertical microvia connections achieved using a unique conductive composite material

Content Provider	IEEE Xplore Digital Library
Author	Matijasevic, G. Gandhi, P. Gallagher, C.
Copyright Year	1998
Description	Author affiliation: Ormet Corp., Carlsbad, CA, USA (Matijasevic, G.)
Abstract	A novel base technology applicable to all major packaging and redistribution elements in an electronic module is presented. A unique polymer/metal composite conductor family based on transient liquid phase sintering (TLPS) can be used for chip package and PWB substrate applications, in interlayer connections, and for SMT assembly. High density multilayer circuits with landless blind and buried vias are fabricated by conductor paste filling of photoimaged dielectrics and thermal processing. Via layers are similarly prepared directly on the inherently planarized circuit layer. Circuit traces as fine as 50 /spl mu/m lines/spaces and vias as small as 75 /spl mu/m have been produced. Building up layers sequentially in this way allows additive fabrication on various materials, including metal substrates. These organic-metallic Ormet/sup (R)/ composites have also been used in interlayer connections between two-sided circuits to form vertical interconnects between circuit pads. This parallel build-up approach uses a standard lamination process to achieve vertical connections. Vias less than 100 /spl mu/m have been used to connect the pads. Fine line two-sided circuits can also be attached as a patch to low density boards to provide localized high density areas. Variations of the composite conductor can also replace solder for surface mount and COB assembly. These reliable, high thermal/electrical conductivity materials are compatible with standard metal finishes of conventional technologies and can be used piecemeal as desired, but the largest reliability and cost benefit is realized when all of the elements are used together.
Starting Page	306
Ending Page	311
File Size	843904
Page Count	6
File Format	PDF
ISBN	0780350901
DOI	10.1109/IEMTIM.1998.704665
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-04-15
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Organizing Committee
Subject Keyword	Circuits Thermal conductivity Conductors Electronic packaging thermal management Dielectric substrates Assembly Inorganic materials Conducting materials Materials reliability Electronics packaging
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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