NDLI: Hardware realization of DC embedding video watermarking technique based on FPGA

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Hardware realization of DC embedding video watermarking technique based on FPGA

Content Provider	IEEE Xplore Digital Library
Author	ElAraby, W.S. Madian, A.H. Ashour, M.A. Wahdan, A.M.
Copyright Year	2010
Description	Author affiliation: Radiation Engineering Department, NCRRT, Egyptian Atomic Energy Authority, Cairo, Egypt (ElAraby, W.S.; Madian, A.H.; Ashour, M.A.) \|\| Faculty of Engineering, Ain-Shams University, Abbassia, Cairo, Egypt (Wahdan, A.M.)
Abstract	In this paper, a video watermark technique is proposed. The proposed technique depends on inserting invisible watermark in Low Frequency DCT domain using pseudo random number (PN) sequence generator for the video frames instead of high or mid band frequency components. This technique has been realized using Matlab and VHDL. The system has been implemented on Xilinx chip XC5VLX330T. The result of implementation shows that maximum frequency 13.61 MHZ. The experimental and implementation results has been demonstrated and discussed.
Starting Page	463
Ending Page	466
File Size	1002931
Page Count	4
File Format	PDF
ISBN	9781612841496
e-ISBN	9781612841519
DOI	10.1109/ICM.2010.5696189
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-19
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Watermarking Clocks Robustness Frequency domain analysis Discrete cosine transforms Generators Manganese DCT VHDL Video
Content Type	Text
Resource Type	Article

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