NDLI: The interlaced carry-arrest adder

Content Provider	IEEE Xplore Digital Library
Author	Fam, A.T.
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering, The State University of New York at Buffalo, 14260, USA (Fam, A.T.)
Abstract	The interlaced carry-arrest adder (ICA) is introduced as a new, fast multioperand adder to compute the sum of four or more numbers. To avoid the need to propagate the carry all the way to the most significant bits, periodic gaps of zeros are created in each of the summands by moving certain pattern of their bits into auxiliary arrays. The pattern of the moved bits is staggered, such that the auxiliary arrays are filled without overlaps and with a periodic pattern of gaps left unfilled such that the resulting auxiliary numbers also have the same staggered zero patterns as the summands. These gaps convert a sum of numbers with arbitrarily large number of bits to independent parallel additions of short pairs of numbers. This is so since any carry bits resulting from the addition of pairs of short numbers are trapped in the gaps. This allows for fast parallel addition that is truly independent of the number of bits of the summands, and depend only on the number of bits in the short numbers added in parallel, and logarithmically on the number of numbers to be added.
Starting Page	120
Ending Page	123
File Size	173264
Page Count	4
File Format	PDF
ISBN	9781612841496
e-ISBN	9781612841519
DOI	10.1109/ICM.2010.5696088
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-19
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adders Nickel Mathematical model Equations Patents Digital arithmetic Logic circuits Parallel Computing Multioperand Interlaced Carry-Arrest Adder Sums Partial Sums Multiplication
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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