NDLI: CUSPARC IP processor: Design, characterization and applications

Content Provider	IEEE Xplore Digital Library
Author	Hussein, E.E.O. Shams, S.I. Ali, M.I. Suleiman, A.A.Z. ElWazeer, K. Sobhy, E.A. Ibrahim, A.A.I. Ibrahim, A.M.G. Khairy, M.S. Fouda, M.F. El-Shafie, A.A. Hareedy, A.H.M. Ahmed, E.A. Zakaria, A.R. El-Galaind, K.M. Sherief, A.A.E. Habib, S.E.
Copyright Year	2010
Description	Author affiliation: Department of Electronics and Communications, Cairo University, Egypt (Hussein, E.E.O.; Shams, S.I.; Ali, M.I.; Suleiman, A.A.Z.; ElWazeer, K.; Sobhy, E.A.; Ibrahim, A.A.I.; Ibrahim, A.M.G.; Khairy, M.S.; Fouda, M.F.; El-Shafie, A.A.; Hareedy, A.H.M.; Ahmed, E.A.; Zakaria, A.R.; El-Galaind, K.M.; Sherief, A.A.E.; Habib, S.E.)
Abstract	In this paper, we introduce the design of an IP processor core code-named CUSPARC for Cairo university SPARC processor. This core is a 32 bit pipelined processor that conforms to SPARC v8 ISA. It is complete with 4 register windows, I and D caches, SRAM and flash memory controller, resolution hardware for the data and branch hazards, interrupts and exception handling, instructions to support I/O transfers, and two standard WISHBONE buses to support high speed and low speed IO transfers. The design was downloaded and tested on different FPGA platforms, in addition to 0.35µm and 0.13µm ASIC technologies. CUSPARC has a promising metric of 0.9663 DMIPS/MHz. A novel debugger tool was developed for validating CUSPARC. This tool facilitates the testing of the processor running complex software loads by invoking Mentor's MODELSIM simulator in the background while maintaining a “simulator-like” GUI in the foreground.
Starting Page	435
Ending Page	438
File Size	217805
Page Count	4
File Format	PDF
ISBN	9781612841496
e-ISBN	9781612841519
DOI	10.1109/ICM.2010.5696181
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-19
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Random access memory Registers Computer architecture Software Real time systems Measurement CUSPARC IP processor processor design SPARC
Content Type	Text
Resource Type	Article

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