NDLI: Generalized power efficient technique for polyphase comb filter in multi-rate digital receivers

Content Provider	IEEE Xplore Digital Library
Author	Ahmed, N.Y. Ashour, M.A. Nassar, A.M.
Copyright Year	2010
Description	Author affiliation: Faculty of engineering, Cairo University, Egypt (Nassar, A.M.) \|\| Microelectronics Design Center, Atomic Energy Authority, Cairo, Egypt (Ahmed, N.Y.; Ashour, M.A.)
Abstract	A generalized power efficient clock distribution technique for the input registers of the polyphase comb decimation filter is presented. A general form of the proposed technique is developed for any integer decimation factor. The Spartan3 low power FPGAs family is used to implement both proposed and conventional comb filters. From the implementation results it is shown that, applying the proposed technique reduces the dynamic power consumption of second and third order polyphase comb filters up to 56.28% and 50.91%, respectively, depending on the decimation factor and the number of quantizer bits. For particular power consumption, the SNR of a second order ΣΔ modulator is increased, using second and third order modified filters, by 19.4 dB and 16.5 dB respectively, depending on the decimation factor and the number of quantizer bits.
Starting Page	116
Ending Page	119
File Size	329503
Page Count	4
File Format	PDF
ISBN	9781612841496
e-ISBN	9781612841519
DOI	10.1109/ICM.2010.5696087
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-19
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Registers Modulation Power demand Clocks Power filters Signal to noise ratio S? modulator Comb Filters Power Consumption Polyphase Decomposition
Content Type	Text
Resource Type	Article

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