NDLI: Low-power multiplierless DCT for image/video coders

Content Provider	IEEE Xplore Digital Library
Author	Byoung-Il Kim Ziavras, S.G.
Copyright Year	2009
Description	Author affiliation: Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, 07102, USA (Byoung-Il Kim; Ziavras, S.G.)
Abstract	A multiplierless discrete cosine transform (DCT) architecture is proposed to improve the power efficiency of image/video coders. Power reduction is achieved by minimizing both the number of arithmetic operations and their bit width. To minimize arithmetic-operation redundancy, our DCT design focuses on Chen's factorization approach and the constant matrix multiplication (CMM) problem. The 8×1 DCT is decomposed using six two-input butterfly networks. Each butterfly is for 2×2 matrix multiplication and requires a maximum of eight adders/subtractors with 13-bit cosine coefficients. Consequently, the proposed 8×1 DCT architecture is composed of 56 adders and subtractors, which represent a reduction of 61.9% and 46.1% in arithmetic operations compared to the conventional NEDA and CORDIC architectures, respectively. To further improve the power efficiency, an adaptive companding scheme is proposed. The proposed DCT architecture was implemented on a Xilinx FPGA. The results from power estimation show that our architecture can reduce the power dissipation by up to 90% compared to conventional multiplierless DCT architectures.
Starting Page	133
Ending Page	136
File Size	359635
Page Count	4
File Format	PDF
ISBN	9781424429752
DOI	10.1109/ISCE.2009.5156873
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-25
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete cosine transforms Computer architecture Arithmetic Coordinate measuring machines Read only memory USA Councils Matrix decomposition Field programmable gate arrays Power dissipation Video coding constant matrix multiplication (CMM) Discrete cosine transform (DCT) multiplierless DCT power dissipation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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