NDLI: A peak current and power pad count reduction tool for system-level IC designers

Content Provider	IEEE Xplore Digital Library
Author	Tsung-Yi Wu Tzi-Wei Kao Shi-Yi Huang Tai-Lun Li How-Rern Lin
Copyright Year	2009
Description	Author affiliation: Dept. of Computer Science and Information Engineering, Da-Yeh University, Changhua, Taiwan (How-Rern Lin) \|\| Department of Electronic Engineering, National Changhua University of Education, Taiwan (Tsung-Yi Wu; Tzi-Wei Kao; Shi-Yi Huang; Tai-Lun Li)
Abstract	In a typical synchronous circuit system, a large peak current occurs near the time of an active clock edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a clock scheme of mixed positive and negative triggering edges rather than one of pure positive (negative) triggering edges. In this paper, we propose a software tool that can assign either a rising triggering edge or a falling triggering edge to each clock of each block of a given system-level design. The goal of the clock-triggering-edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.
Starting Page	128
Ending Page	129
File Size	212249
Page Count	2
File Format	PDF
ISBN	9781424429752
DOI	10.1109/ISCE.2009.5156905
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-25
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Flip-flops Voltage Logic design Switching circuits Delay Design engineering Power engineering and energy Aggregates Software tools
Content Type	Text
Resource Type	Article

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