NDLI: Jitter testing technique and results at VC-4 desynchronizer output of SDH equipment

Content Provider	IEEE Xplore Digital Library
Author	Bregni, S. D'Agrosa, M. Valtriani, L.
Copyright Year	1994
Description	Author affiliation: Network Technol. Div., SIRTI S.p.A., Milan, Italy (Bregni, S.; D'Agrosa, M.; Valtriani, L.)
Abstract	Many parameters have to be taken into account when testing an SDH (Synchronous Digital Hierarchy) apparatus. Specifications relative to jitter and wander generation, at the output of desynchronizer systems, represents one of the hottest topics in characterising SDH equipment. Among the many factors involved, pointer justifications, due to phase variations between the clock of the received timing signal and the internal clock of SDH equipment, play indeed a primary role in phase noise accumulation. This paper deals with the effects of AU pointer justifications, combined with the asynchronous mapping of plesiochronous tributaries in VC-4, in the phase rebuilding process of the demapped tributaries. Moreover, a detailed description of the testing technique is provided. Two different kinds of test have been designed for measuring and analysing phase transients from O Hz on, namely dynamic jitter measurement configuration and static jitter measurement configuration. Some results, obtained by applying this technique on different suppliers piece of equipment, are presented and their relative impact on normative is highlighted.
Starting Page	1407
Ending Page	1410
File Size	435495
Page Count	4
File Format	PDF
ISBN	0780318803
DOI	10.1109/IMTC.1994.352159
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-10
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Jitter Testing Synchronous digital hierarchy Phase measurement Clocks Transient analysis Character generation Timing Phase noise Gold
Content Type	Text
Resource Type	Article

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