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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Liberatore, A. Manetti, S. Piccirilli, M.C. |
| Copyright Year | 1994 |
| Description | Author affiliation: Dept. of Electron. Eng., Florence Univ., Italy (Liberatore, A.; Manetti, S.; Piccirilli, M.C.) |
| Abstract | Testing an electronic circuit is a vital part of its overall design and fabrication process. This problem is even going to be more critical with technology improvements and with the coexistence on a chip of analog and digital components. In fact the testing of mixed signal microsystems is very difficult compared to digital only devices. They do not lend themselves to earlier and simpler test routines. The entire mixed signal segment is hampered by the lack of design for testability methodologies and tools. In this field the concept of analog circuit testability is of fundamental importance. The aim of this work is to present a new symbolic approach for testability measurement of analog networks. The new method presents noteworthy advantages from a computational point of view with respect to previous techniques. In fact it does not require the computation of the sensitivities of the network functions but it is based only on the study of the network function symbolic coefficients. The new approach allows also the formulation of simple necessary conditions for maximum testability based only on the order of the network functions. |
| Starting Page | 193 |
| Ending Page | 196 |
| File Size | 447639 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780318803 |
| DOI | 10.1109/IMTC.1994.352094 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1994-05-10 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit testing Analog circuits Transfer functions Semiconductor device measurement Electronic equipment testing Electronic circuits Process design Fabrication Design for testability Computer networks |
| Content Type | Text |
| Resource Type | Article |
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