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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Low, P. |
| Copyright Year | 1994 |
| Description | Author affiliation: Inst. fur Elektrische Messtech., Tech. Univ. Wien, Austria (Low, P.) |
| Abstract | This paper introduces the design of a vertically structured subranging A/D-Converter. The vertically structured analog subranging circuits combined with the most common flash ADC led to the development of a converter for high conversion rates up to a resolution of 12 Bit. The compensation of the analog circuits reduces linearity errors to a minimum. Special attention has been paid on the differential architecture of the analog subranging circuits. The major advantage of this architecture is the improvement of the SNR and the reduction of errors caused by symmetrical parasitic impedances. New results are presented with a hybrid test circuit for a 10 Bit 30 Ms/s converter. |
| Starting Page | 890 |
| Ending Page | 893 |
| File Size | 366247 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780318803 |
| DOI | 10.1109/IMTC.1994.351966 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1994-05-10 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Linearity Circuit testing Digital circuits Operational amplifiers Voltage Switches Analog circuits Impedance Digital signal processing Signal resolution |
| Content Type | Text |
| Resource Type | Article |
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