NDLI: FPGA-based fault tolerant scheme with reduced extra-sensor number for WECS with DFIG

Content Provider	IEEE Xplore Digital Library
Author	Shahbazi, M. Gaillard, A. Poure, P. Zolghadri, M.R.
Copyright Year	2011
Description	Author affiliation: Center of Excellence in Power System Management & Control (CEPSMC), Sharif University of Technology, Tehran, Iran (Zolghadri, M.R.) \|\| Laboratoire d'Instrumentation Electronique de Nancy, LIEN, Université de Nancy, France (Poure, P.) \|\| Groupe de Recherche en Electrotechnique et Electronique de Nancy, GREEN, Université de Nancy, France (Shahbazi, M.; Gaillard, A.)
Abstract	Fast fault detection and converter reconfiguration is necessary for fault tolerant doubly fed induction generator (DFIG) in wind energy conversion systems (WECS) to prevent further damage and to make possible the continuity of service. Extra sensors are needed in order to detect the faults rapidly. In this paper, a very fast FPGA-based fault detection scheme is presented that minimizes the number of additional voltage sensors. A fault tolerant converter topology for this application is studied. Control and fault detection system are implemented on a single FPGA and Hardware in the Loop experiments are performed to evaluate the proposed detection scheme, the digital controller and the fault tolerant structure.
Starting Page	1595
Ending Page	1601
File Size	978552
Page Count	7
File Format	PDF
ISBN	9781424493104
e-ISBN	9781424493128
e-ISBN	9781424493111
DOI	10.1109/ISIE.2011.5984398
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-27
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Leg Fault tolerance Fault tolerant systems Voltage measurement Fault detection Field programmable gate arrays Circuit faults Hardware in loop (HIL) Field-Programmable Gate Array (FPGA) Fault tolerant converter
Content Type	Text
Resource Type	Article

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