NDLI: RSR: a new rectilinear Steiner minimum tree approximation for FPGA placement and global routing

Content Provider	IEEE Xplore Digital Library
Author	de Vincente, J. Lanchares, J. Hermida, R.
Copyright Year	1998
Description	Author affiliation: ETSIAN, Madrid, Spain (de Vincente, J.)
Abstract	The work combines FPGA placement and global routing phases in a single phase, taking advantage of the interrelations between them both. The authors have developed rectilinear Steiner regions (RSR), a new fast algorithm to approximate the rectilinear Steiner minimum tree (RSMT) of each multi-terminal net. The search of placement solutions is performed in three simulated annealing optimization phases, guided by different objective functions. The first one uses a semi-perimeter classic metric to reduce the length of the nets. The second one estimates more precisely the length of the nets with RSR algorithm. The third stage measures the congestion making a fast routing of RSR regions in each placement iteration. They have also developed an RSR-based global router. This optimization method has been applied for the placement and global routing of a set of benchmark circuits. The layouts obtained, require equal or fewer routing tracks per channel segment than those produced by other tools appeared in the literature, that only optimize the semi-perimeter classic placement cost function.
Starting Page	192
Ending Page	195
File Size	407087
Page Count	4
File Format	PDF
ISBN	0818686464
ISSN	10896503
DOI	10.1109/EURMIC.1998.711797
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-08-27
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Steiner trees Field programmable gate arrays Routing Simulated annealing Cost function Wires Heuristic algorithms Optimization methods Circuit simulation Surface-mount technology
Content Type	Text
Resource Type	Article

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