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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sang-Joon Lee Raahemifar, K. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON (Sang-Joon Lee; Raahemifar, K.) |
| Abstract | Field programmable gate array (FPGA) is a programmable chip that can be used to quickly implement any digital circuits. Placement is an important part of FPGA design step which determines physical arrangement of the logic blocks in the FPGA. The quality of placement of logic blocks determines overall performance of the logic implemented in the FPGA. In this paper, a number of placement optimization techniques are reviewed; min-cut, quadratic, simulated annealing, and a hybrid approach of using genetic algorithm with simulated annealing technique. The methodology of each optimization technique is presented and its advantages and disadvantages are evaluated. Overall, the hybrid approach of using genetic algorithm with simulated annealing technique produces best result, reaching a global optimal solution. The hybrid approach of using genetic algorithm and simulated annealing optimization technique is implemented using MATLAB and its results are presented using a wire-length-driven placement as cost function. |
| Starting Page | 001981 |
| Ending Page | 001986 |
| File Size | 176400 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424416424 |
| ISSN | 08407789 |
| DOI | 10.1109/CCECE.2008.4564891 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-04 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Optimization methods Simulated annealing Genetic algorithms Timing Programmable logic arrays Cost function Digital circuits Routing Circuit simulation genetic algorithms optimization methods routing quadratic programming simulated annealing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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