NDLI: The latency hiding effectiveness of decoupled access/execute processors

Content Provider	IEEE Xplore Digital Library
Author	Parcerisa, J.-M. Gonzalez, A.
Copyright Year	1998
Description	Author affiliation: Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain (Parcerisa, J.-M.)
Abstract	Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide-issue processors due to the increasing penalties that wire delays cause in the issue logic. The main target of out-of-order execution is to hide functional unit latencies and memory latency. However, the former can be quite effectively handled at compile time and this observation is one of the main arguments for the emerging EPIC architectures. In this paper, we demonstrate that a decoupled access/execute organization is very effective at hiding memory latency, even when it is very long. This paper presents a thorough evaluation of such processor organization. First, a generic decoupled access/execute architecture is defined and evaluated. Then the benefits of a lockup-free cache, control speculation and a store-load bypass mechanism under such an architecture are evaluated. Our analysis indicates that memory latency can be almost completely hidden by such techniques.
Starting Page	293
Ending Page	300
File Size	892693
Page Count	8
File Format	PDF
ISBN	0818686464
ISSN	10896503
DOI	10.1109/EURMIC.1998.711813
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-08-27
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Out of order Clocks Parallel processing Prefetching Dynamic scheduling Force control Wire Logic Pipelines
Content Type	Text
Resource Type	Article

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The Latency Hiding Effectiveness of Decoupled Access/Execute Processors (1998)

The Latency Hiding Effectiveness of Decoupled Access/Execute Processors (1998)

The Latency Hiding Effectiveness of Decoupled Access/Execute Processors (1998)

Multithreaded decoupled access/execute processors (1997).

Performance evaluation of Cascade ALU architecture for asynchronous super-scalar processors

Static scheduling for out-of-order instruction issue processors

A comparison of superscalar and decoupled access/execute architectures

A comparison of data prefetching on an access decoupled and superscalar machine

The synergy of multithreading and access/execute decoupling

The latency hiding effectiveness of decoupled access/execute processors

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