NDLI: Register allocation with simultaneous BIST intrusion

Content Provider	IEEE Xplore Digital Library
Author	Olcoz, K. Tirado, J.F.
Copyright Year	1998
Description	Author affiliation: Dept. de Arquitectura de Comput. y Autom., Univ. Complutense de Madrid, Spain (Olcoz, K.)
Abstract	We present an algorithm for register allocation of self-testable data paths, which have some test registers. Classical approaches synthesizing minimum area data paths and then adding minimum number of test registers to it do not lead to data paths with minimum global area. Testability consideration during synthesis makes design search more efficient and hence can possibly find self-testable data paths with minimum area. We present a model to evaluate the testability of data paths that is used when register allocation is being done. Moreover, we propose some heuristics that guide the design space search during allocation, to save exploration time. Each allocation decision is made according to testability and area increments that the alternatives for allocation produce, so that alternatives increasing area are only chosen when the testability gain is worth it.
Starting Page	99
Ending Page	106
File Size	842142
Page Count	8
File Format	PDF
ISBN	0818686464
ISSN	10896503
DOI	10.1109/EURMIC.1998.711783
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-08-27
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit testing Automatic testing Registers Logic testing Space technology High level synthesis Integrated circuit testing Circuit synthesis Performance evaluation
Content Type	Text
Resource Type	Article

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