NDLI: Revolver: a high-performance MIMD architecture for collision free computing

Content Provider	IEEE Xplore Digital Library
Author	Oberg, J. Ellervee, P.
Copyright Year	1998
Description	Author affiliation: Electr. Syst. Design Lab., R. Inst. of Technol., Stockholm, Sweden (Oberg, J.)
Abstract	One of the main bottlenecks when using massively parallel processors, both RISC and CISC, and VLIW style processors has been the identification of potential parallelism in the tasks. Multi-threaded techniques for exploiting instruction- and data-level parallelism have gained renewed interest since high degrees of pipelining, caused by the increasing clock frequencies, introduce extra dependencies between instructions. Sophisticated methods implementing branch prediction and pipeline flushing during interrupts must be adopted which in addition puts more requirements onto the compilers. We present an interleaved processing architecture we call the Revolver Architecture together with a technique we call register file folding, which relieves the MIMD architecture of these dependencies to allow for collision free computing. We also discuss the implementation of the Revolver as a multi-threaded processor core, based on our presented techniques, together with some architectural strategies for implementing the Revolver Architecture as a DSP core.
Starting Page	301
Ending Page	308
File Size	706016
Page Count	8
File Format	PDF
ISBN	0818686464
ISSN	10896503
DOI	10.1109/EURMIC.1998.711814
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-08-27
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Pipeline processing Yarn Hardware Reduced instruction set computing Parallel processing Clocks Registers Assembly Computer aided instruction
Content Type	Text
Resource Type	Article

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