NDLI: Multiplier-less FIR digital filters using programmable sum-of-power-of-two (SOPOT) coefficients

Content Provider	IEEE Xplore Digital Library
Author	Yeung, K.S. Chan, S.C.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Electron. Eng., Hong Kong Univ., China (Yeung, K.S.; Chan, S.C.)
Abstract	This paper proposes a new architecture for the implementation of multiplier-less FIR digital filters with programmable sum-of-powers-of-two (SOPOT) or canonical signed digit (CSD) coefficient representations. The multiplier-less FIR filter is implemented as the direct form structure with the filter coefficients represented as SOPOT representation, which can be realized as limited number of shifts and additions. Traditional VLSI implementations of multiplier-less FIR filters are usually hardwired and the filter coefficients cannot be programmed online. The proposed architecture is very modular in the structure and it can be connected to implement the multiplier-less FIR filter with arbitrary filter order and SOPOT terms using programmable SOPOT coefficients. The structure is also pipelined to achieve a high data throughput rate at low hardware cost. The proposed architecture was implemented and tested using the Altera FLEX 10K Field Programmable Gate Arrays (FPGA). The finite wordlength effect such as signal roundoff and overflow errors are also taken into account. A design example is given to demonstrate the feasibility of the proposed architecture.
Sponsorship	Croucher Found. IEEE Hong Kong Section Electron Devices Soc. Chung Chi College, CUHK IEEE Comput. Soc. IEEE Electron Devices Soc
Starting Page	78
Ending Page	84
File Size	391392
Page Count	7
File Format	PDF
ISBN	0780375742
DOI	10.1109/FPT.2002.1188667
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Digital filters Hardware Throughput Field programmable gate arrays Costs Testing Finite wordlength effects Digital signal processing Digital communication
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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