NDLI: Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards

Content Provider	IEEE Xplore Digital Library
Author	Jain, S.C. Kumar, A. Kumar, S.
Copyright Year	2002
Description	Author affiliation: EE Dept., Eng. Coll., Kota, India (Jain, S.C.)
Abstract	In rapid prototyping system application, any large digital circuit can be implemented onto Multi-FPGA Board(MFB). Key MFB architectural feature is its inter-FPGA connections consisting of fixed connections(FC) i.e. FPGA-FPGA connections and programmable connections(PC) i.e. FPGA-programmable switch like FPID-FPGA. MFBs consisting of both the types of connections are known as hybrid MFBs. Since, PC requires two wires as against one wire in FC, MFB must have minimum number of PCs to keep fabrication easy. In partitioned circuit, multi-terminal nets (MTNs) are distributed over one or more circuit parts. When each circuit part is implemented over one FPGA, the MTNs between circuit parts will be routed over PCs and FCs between corresponding FPGAs. Multi-hop routers are used to minimize the use of PCs, but they increase source to sink delay with increasing number of hops. A generic multi-hop router to route two-terminal nets, which obeys the given limit on hops, was presented in our previous work [2002]. In this paper, we extend the same to route multi-terminal nets.
Sponsorship	Croucher Found. IEEE Hong Kong Section Electron Devices Soc. Chung Chi College, CUHK IEEE Comput. Soc. IEEE Electron Devices Soc
Starting Page	298
Ending Page	301
File Size	242073
Page Count	4
File Format	PDF
ISBN	0780375742
DOI	10.1109/FPT.2002.1188696
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Field programmable gate arrays Personal communication networks Delay Switches Wire Digital circuits Circuit topology Logic circuits Integrated circuit interconnections
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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