NDLI: A system level implementation of Rijndael on a memory-slot based FPGA card

Content Provider	IEEE Xplore Digital Library
Author	Tong, D.K.Y. Pui Sze Lo Kin Hong Lee Leong, P.H.W.
Copyright Year	2002
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China (Tong, D.K.Y.; Pui Sze Lo; Kin Hong Lee; Leong, P.H.W.)
Abstract	This paper describes system level issues encountered in a high performance implementation of a Rijndael encryption core on a memory-slot based reconfigurable computing platform called Pilchard. The Rijndael algorithm was adopted in 2000 by the US National Institute of Standards and Technology (NIST) as the Advanced Encryption Standard (AES). In the implementation of Rijndael, changing the number of unrolled rounds in the encryption core can affect the performance of the system. It is shown that for the design presented, the highest performance of 755 Mbit/sec was achieved by implementing a core with a single round. Although it is relatively easy to implement a high performance core on an FPGA, due to I/O bottlenecks, achieving high system level performance is more difficult. In order to optimize the performance of the host/FPGA interface, special instructions from the Intel Pentium III streaming SIMD extensions (SSE) along with write-combining memory operations were used. These features enabled the measured throughput of the AES core to reach 445 Mbit/sec which, although still slower than the AES core, was double that of an unoptimized interface.
Sponsorship	Croucher Found. IEEE Hong Kong Section Electron Devices Soc. Chung Chi College, CUHK IEEE Comput. Soc. IEEE Electron Devices Soc
Starting Page	102
Ending Page	109
File Size	509228
Page Count	8
File Format	PDF
ISBN	0780375742
DOI	10.1109/FPT.2002.1188670
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Cryptography Throughput NIST Computer science Peak to average power ratio High performance computing Government Hardware Engines
Content Type	Text
Resource Type	Article

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