NDLI: FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator

Content Provider	IEEE Xplore Digital Library
Author	Ying Yi Woods, R.
Copyright Year	2002
Description	Author affiliation: Sch. of Electr. & Electron. Eng., Queen's Univ., Belfast, UK (Ying Yi; Woods, R.)
Abstract	A system level design framework for FPGA-based DSP design is presented. The design flow utilizes System Generator, a system level tool developed by Xilinx, and links it to an "in-house" architectural synthesis tool, IRIS. Whilst System Generator allows FPGA-based Intellectual Property (IP) cores to be incorporated into the design flow, it does not address the timing and latency problems introduced by the cores which can be considerable, particularly when the cores are pipelined. These problems are addressed by the IRIS synthesis tool. The paper describes the tools, their interaction and illustrates the flow using an 8-tap Transpose-Form Retimed Delayed LMS (TF-RDLMS) adaptive filter.
Sponsorship	Croucher Found. IEEE Hong Kong Section Electron Devices Soc. Chung Chi College, CUHK IEEE Comput. Soc. IEEE Electron Devices Soc
Starting Page	85
Ending Page	92
File Size	503319
Page Count	8
File Format	PDF
ISBN	0780375742
DOI	10.1109/FPT.2002.1188668
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-level design Iris Field programmable gate arrays Digital signal processing chips Algorithm design and analysis Digital signal processing Hardware Mathematical model Delay Circuit synthesis
Content Type	Text
Resource Type	Article

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