NDLI: Implementation of an FPGA based accelerator for virtual private networks

Content Provider	IEEE Xplore Digital Library
Author	Cheung, O.Y.H. Leong, P.H.W.
Copyright Year	2002
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China (Cheung, O.Y.H.; Leong, P.H.W.)
Abstract	Virtual Private Networks (VPN) are becoming increasingly popular network architectures for corporate networks. As VPNs are built on the Internet infrastructure, the data exchange among different local area networks will be passed through the Internet and thus can be easily eavesdropped, masqueraded, etc. Therefore, certain security measures must be used to deal with these privacy issues. The Internet Protocol Security (IPSec) by the Internet Engineering Task Force (IETF) addresses the abovementioned security issues and the Free Secure Wide Area Network (FreeS/WAN) is an open source software implementation of IPSec for Linux which uses triple-DES as the default encryption mode. As shown in this paper, the performance of FreeS/WAN with IPSec is 50% of that without encryption. In order to improve its performance, a field programmable gate array (FPGA) based triple-DES accelerator was built on a reconfigurable computing development platform called Pilchard and achieved a throughput of more than 120 Mb/sec for triple-DES in cipher-block chaining mode, a speedup of 3 over a software implementation, Measurements show that an FPGA-accelerated FreeS/WAN offers a 30% speedup for the TCP protocol over the original software library.
Sponsorship	Croucher Found. IEEE Hong Kong Section Electron Devices Soc. Chung Chi College, CUHK IEEE Comput. Soc. IEEE Electron Devices Soc
Starting Page	34
Ending Page	41
File Size	419572
Page Count	8
File Format	PDF
ISBN	0780375742
DOI	10.1109/FPT.2002.1188662
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Virtual private networks IP networks Wide area networks Data security Protocols Cryptography Local area networks Privacy Open source software
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An FPGA network architecture for accelerating 3DES - CBC

Implementation of an FPGA Based Accelerator for Virtual Private Networks (2002)

A network security system model based on FPGA

Secure remote reconfiguration of an FPGA-based embedded system

Secure FPGA configuration architecture preventing system downgrade

A versatile UDP/IP based PC ↔ FPGA communication platform

Implementation of an fpga based accelerator for virtual private networks (2002).

FPGA implementation of MD5 hash algorithm

Secure communication protocol using embedded devices based on FPGA

Implementation of an FPGA based accelerator for virtual private networks

Similar Documents

An FPGA network architecture for accelerating 3DES - CBC

Implementation of an FPGA Based Accelerator for Virtual Private Networks (2002)

A network security system model based on FPGA

Secure remote reconfiguration of an FPGA-based embedded system

Secure FPGA configuration architecture preventing system downgrade

A versatile UDP/IP based PC ↔ FPGA communication platform

Implementation of an fpga based accelerator for virtual private networks (2002).

FPGA implementation of MD5 hash algorithm

Secure communication protocol using embedded devices based on FPGA

Implementation of an FPGA based accelerator for virtual private networks