NDLI: Large dynamic range high resolution digital delay generator based on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Yan Song Hao Liang Lei Zhou Jiye Du Jiming Ma Zhiqin Yue
Copyright Year	2011
Description	Author affiliation: Northwest Institute of Nuclear, Technology, Xi'an 710024, China (Jiye Du; Jiming Ma; Zhiqin Yue) \|\| Hefei National Laboratory for Physical Sciences at Microscale and Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China (Lei Zhou) \|\| State Key Laboratory of Particle Detection & Electronics, Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China (Yan Song; Hao Liang)
Abstract	A novel digital delay generator (DDG) based on FPGA was designed with 4.4ms range and 65ps resolution. The time-to-digital conversion (TDC) utilizing dual tapped delay lines was implemented in the FPGA to accurately measure the time interval between the rising edge of the FPGA global clock and the input trigger pulse. And the time interval was compensated in the following circuits by a AD9501 chip. The counter in the FPGA delays coarse time and another AD9501 chip delays fine time. To increase the accuracy, self-test block was developed in the FPGA to avoid the deviation induced from bad INL and DNL of AD9501 chips. Finally, the jitter of the system tested by TEK (TDS7404) oscilloscope was 400ps.
Starting Page	2116
Ending Page	2118
File Size	481491
Page Count	3
File Format	PDF
ISBN	9781457703201
e-ISBN	9781457703218
DOI	10.1109/ICECC.2011.6067814
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-09
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	TDC AD9501 FPGA Delay lines Built-in self-test Generators Digital Delay Generator Delay Field programmable gate arrays Signal resolution Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in